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Renesas Electronics /R7FA6M3AH /SDHI0 /SD_CLK_CTRL

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Interpret as SD_CLK_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0x00)CLKSEL0 (0)CLKEN 0 (0)CLKCTRLEN

CLKSEL=0x00, CLKCTRLEN=0, CLKEN=0

Description

SD Clock Control Register

Fields

CLKSEL

SDHI Clock Frequency Select

0 (others): Settings prohibited.

0 (0x00): PCLKA divided by 2

1 (0x01): PCLKA divided by 4

2 (0x02): PCLKA divided by 8

4 (0x04): PCLKA divided by 16

8 (0x08): PCLKA divided by 32

16 (0x10): PCLKA divided by 64

32 (0x20): PCLKA divided by 128

64 (0x40): PCLKA divided by 256

128 (0x80): PCLKA divided by 512
CLKEN

SD/MMC Clock Output Control Enable

0 (0): SD/MMC Clock output is disabled. The SDCLK signal is fixed 0.

1 (1): SD/MMC Clock output is enabled.
CLKCTRLEN

SD/MMC Clock Output Automatic Control Enable

0 (0): Automatic control for SD/MMC Clock output is disabled.

1 (1): Automatic control for SD/MMC Clock output is enabled.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data